1. Field of the Invention
The present invention relates to a plating apparatus, and more particularly to a plating apparatus used for filling interconnect recesses formed in a substrate, such as a semiconductor wafer, with an electrical conductor (interconnect material), such as copper or silver, so as to form interconnects.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a metallic material for forming interconnect circuits on a substrate, there is an eminent movement towards using copper (Cu) that has a low electric resistivity and high electromigration resistance. Copper interconnects are generally formed by filling copper into fine interconnect recesses formed in a surface of a substrate. There are various known techniques for forming such copper interconnects, including CVD, sputtering, and plating. According to any such technique, a copper film is formed in a substantially entire surface of a substrate, followed by removal of unnecessary copper by performing chemical mechanical polishing (CMP).
FIGS. 1A through 1C illustrate, in a sequence of process steps, an example of forming such a substrate W having copper interconnects. First, as shown in FIG. 1A, an insulating film 2, such as an oxide film of SiO2 or a Low-k material film, is deposited on a conductive layer 1a on a semiconductor base 1 having formed semiconductor devices. Contact holes 3 and trenches 4 for interconnect recesses are formed in the insulating film 2 by performing a lithography/etching technique. Thereafter, a barrier layer 5 of Ta, TaN, TiN, WN, SiTiN, CoWP, CoWB, or the like is formed on the insulating film 2, and a seed layer (conductive film) 7 as an electric supply layer for electroplating is formed on the barrier layer 5.
Then, as shown in FIG. 1B, copper plating is performed onto a surface of the seed layer 7 of the substrate W to fill the contact holes 3 and the trenches 4 with copper and, at the same time, deposit a copper film 6 on the insulating layer 2. Thereafter, the copper film 6, the seed layer 7 and the barrier layer 5 on the insulating film 2 are removed by performing chemical mechanical polishing (CMP) so as to make the surface of the copper filled in the contact holes 3 and the trenches 4 and the surface of the insulating film 2 lie substantially on the same plane. Interconnects composed of the copper film 6, as shown in FIG. 1C, are thus formed in the insulating film 2.
In forming copper interconnects in an insulating film, pre-formation of a seed layer having a thickness of about 60 to 100 nm on the surfaces of trenches and contact holes formed in the insulating film is widely practiced, as described above. A seed layer is a conductive film for flowing a current to a substrate immediately after the start of plating when a copper film is not sufficiently grown. A seed layer is formed prior to plating by sputtering or the like.
In recent years, the sizes of trenches and contact holes are becoming smaller for the purpose of increasing the integration density of semiconductor devices. With the trend toward smaller-sized trenches and contact holes, the following problem has become serious: When a seed layer 7 having a conventional thickness is formed on a surface of a barrier layer 5 which covers surfaces of smaller-sized trenches 4 and contact holes 3, the seed layer 7 may hand considerably inwardly over the openings of the trenches 4 and contact holes 3 such that it blocks in the openings, thus narrowing the openings, as shown in FIG. 2. This impedes electrodeposition of copper in the trenches 4 and contact holes 3 in the next plating step, whereby voids are likely to be formed within the interconnects formed of a plated film, lowering the reliability of the interconnects.
One method to solve the above problem is to make a thickness of a seed layer 7 smaller. Plating on a thinner seed layer 7, however, entails the following problem. As shown in FIG. 3, the sheet resistance R2 of the seed layer 7 between its center and its peripheral electricity-feeding portion becomes relatively higher than the resistance R1 of a plating solution 202 present between an anode 200, connected to the anode of a plating power source 206, and the surface seed layer (conductive film) 7 of a substrate W, connected to the cathode of the plating power source 206 (R1<<R2). As a result, a higher current flows in the peripheral region, having a lower electric resistance, of the seed layer 7. Accordingly, the plated film produced by plating has a film thickness profile as shown in FIG. 4, indicating a thin film in the central region of the substrate and a gradually thicker film in the peripheral region of the substrate. When carrying out CMP or the like of the substrate, having such a thick plated film formed in the peripheral region, to remove an extra plated film and flatten an entire surface of the substrate, a longer processing (polishing) time is needed in a CMP process or the like, thus lowering the productivity.
A known method for improving such an uneven thickness of a plated film is to interpose a high resistance structure 204a between the anode 200 and the substrate, as shown in FIG. 5. The higher resistance structure 204a allows the plating solution 202 to penetrate into it through complicated paths, and hence has a higher resistance than the resistance of the plating solution 202 itself. A thickness of the high-resistance structure 204a is made to increase gradually with the distance from the center to the periphery so as to incline the electric resistance distribution in the radial direction of the substrate, thereby making the current density distribution uniform over the substrate. Another known method is to interpose an insulating ring 206 between the anode 200 and a flat plate-shaped high-resistance structure 204b in their peripheral regions, as shown in FIG. 6. The shielding of electric current by the insulating ring 206 can prevent an excessive current from flowing locally (peripheral region of the substrate).
These methods, however, necessitate additionally preparing, for example, a high-resistance structure 204a having a different thickness distribution or an insulating ring 206 having a different width, and replacing the old one with such new one whenever a thickness of a plated film obtained by plating falls out of its standard. This not only increases the component cost, but also entails downtime in an actual semiconductor device manufacturing process, resulting in a lowered throughput.
A method has also been proposed in which a lattice-like or net-like auxiliary cathode, which can control the current proportion, is disposed between a substrate and an anode, and a voltage is applied between the anode and the substrate, and also between the anode and the auxiliary cathode in carrying out plating, thereby improving the uniformity of a thickness of a plated film (see Japanese Patent Laid-Open Publication No. 2006-89810). However, in view of the fact that such auxiliary cathode covers the entire surface (surface to be plated) of the substrate, it is considered that the uniformity of a plated film cannot be improved selectively in the vicinity of a cathode contact, i.e., in the outermost peripheral region of the substrate, where a plated film is likely to become thick due to the concentration of electric current.